As seen in this table, Mark Horowitz, PhD shows how the amount of energy needed for a 32bit SRAM read is 25x more than the energy needed for a 8bit multiply function. CortiCore architecture reduces the non IP system memory access to once per input data and never does any writes to the non-IP memory, inspite of low (256KB) internal memory.
- Scalable RTL via parameters for performance and power
- Number of ALU
- Number of clusters
- Activation memory size per cluster (Local mem –can be 256KB, 512KB typical)
- DDR or No DDR – external memory
- Internal system memory
- External shared memory (optional)